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Basic Instructions
A Little History
A common programming language used in PLC's is called Ladder Logic. Ladder Logic was developed years ago to help electricians adapt to PLC's. Ladder logic is still widely in use today although this language appears to be weakening. Ladder logic is similar to Assembly Language in many ways which was widely used to program computers years ago. Since then, higher level languages such as PASCAL have come along. In the last few years we have seen a more Object Oriented approach to programming in languages such as Java. The ControlLogix processor seems to be following the Object Oriented approach with it's User Defined data types (UDTs), and event driven tasks.
Here are some of the instructions available in Ladder Logic:
Examine If Closed (XIC)
You will find that most instructions in the SLC, PLC-5, and ControlLogix consist of three character pneumonics. The XIC looks at a given bit of memory in the processor. If this bit is on, then the XIC will intensify indicating logical continuity through the instruction. Here is what the XIC looks like in logic.

Examine If Open (XIO)
The XIO is just the opposite of the XIC instruction. The XIO looks at a bit in memory. If the bit is a 0, then the XIO is true. It will intensify indicating logical continuity through the instruction, and the next instruction in the rung will be examined. This is usually referred to as a NOT instruction because the address the instruction points to must NOT be on for the instruction to be true. Here is an example of how the XIO will appear in ladder logic:

In the above example, you can see that as soon as the Main Pump Switch is shut off, a bit is set to run the backup pump.
Output To Energize (OTE)
The output to energize simply turns a bit on when it is evaluated as true, and shuts a bit off when the instruction is evaluated as false. Using the same address on an OTE in two different places in the program is considered bad programming practice. The two OTE's can interfere with each other, and makes troubleshooting difficult.
Below you will find two different states of the same rung. The first state shows the rung as false, so a zero is written to B3:1/0. The second state is true, and a 1 will be written to B3:1/0.
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Output To Latch (OTL) and Output To Unlatch (OTU)
The Output To Latch instruction will write a 1 to it's address when true. When the OTL goes false again, the output address will remain a 1 until another instruction such as the Output to Unlatch shuts it back off. This is true even if the processor powers down, and is brought back up!! You must use caution when using the Latch/Unlatch when controlling real world devices. Here is what the Latch/Unlatch will look like in logic:

If the output address is off, both the latch and unlatch instructions are not intensified, but once the bit is turned on, you will see both the latch and unlatch intensified even though both inputs are shut off.

Due to the processor scan cycle, since the unlatch is placed after the latch, if both inputs were to go true, the Unlatch instruction would win, and the output address will be shut off. If the latch was after the unlatch, then the latch would be the last instruction scanned, and therefore the bit would be left in the energized state.